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as91l1003u july 2004 3-port jtag gateway description the as91l1 003 u is a on e to 3-port jtag gateway. it partition s a singl e jtag chain into three sepa rat e chai ns. th ese sep a rate chain s can be optionally configu r ed to operate a s a singl e chai n. the as91l 1003 u devi c e i s used to provide enhanced capabilit ies to the standard ieee1149.1. it enables the ieee1149. 1 interface to be used in a true multi-drop e n viron m ent without any addition al sign als. t h is multi-dro p cap ability enabl es the stand ard iee e 1149.1 inte rface to be use d not ju st for sta nd al o ne printe d ci rcuit bo ard (p cb ) t e st i ng, but co mplet e sy st em t e st in g inclu d ing all pcbs withi n a system back plan e environ ment. the as91l1003u provid es the capability of partitionin g the pcb into multiple smalle r ieee1149.1 scan chain s totally under software control. partitioning the iee e 1149.1 chai ns on th e pcb ha s se veral b enefit s, which in cl ude e a si er fault diagnost i cs ca pabilities, as a fault on one of the ieee1149.1 local scan ports (ls p s) do es not ren d e r the pcb u n - testabl e, faster fla s h prog ram m ing on the pcb?s an d removal of ieee1149.1 signal loadi ng i s sue s . all of the proto c ol s req u ired for addressin g th e as91l1 003 u devi c e via the multi- dro p capa bili ty and the p r otocol s fo r configuri ng whi c h of th e thre e ieee1149.1 lsps of th e as91l10 03 u are to be u s ed, is h andl ed via the 3 rd party atpg tools fro m vendors li ke asset- intertech an d jtag te chn o logie s . in a multi-drop environ ment, it is also po ssi ble t o pe rform interconnec t tes t s between multiple p c bs within the sy stem t hus extendin g the inte rco nne ct test s to the back pl ane itself. key features device multi - drop a d d r e s sable via t he ieee 1149.1 p r oto c ol suppo rt for 3 local scan chain s ad dre s sabl e via the ieee 1149.1 interface suppo rt for pass-t hro ugh ? suppo rt for the ieee 114 9.1 userco de inst ru ct ion suppo rt for status inst ructio n ena b ling n o n - intrusive m o n i toring of the system card local sca n p o rt (lsp) ena ble si gnal p r o v ides the ability to use non ieee 1149.1 compliant devices that requi re jtag enabl e signal provides the ability to initiate self-test on a remote p c b via a standard ieee 1149.1 comm and suppo rt for jtag te chnolo g ies a u towr ? feature pinout and feature set compatible (complete se con d sou r ce) wit h t he fire cro n jts 0 3 u device available in a 100-pi n lqf p or a 100-pi n fpbga lead free pa ckag e device block diagram d e vi ce s e le c t io n l ogi c lo c a l s c an p o r t p a rk / u n - p a rk s y n c log i c 1 1 49. 1 t a p c ont r o l l er and b o un da r y r e g i s t er s e l e c t i o n lo gi c pa s s t h r ough lo gi c & loc al s c an po r t c o nnec t i on /c o n f i g lo g i c l sp1 l sp2 l sp3 st a t u s d a t a u s er c ode da t a d e vi ce addr es s p a s s t h r ough e n abl e p r i m ar y 1149. 1 jt a g i n t e r f a c e figure 1 - as91l10 03 u dev i ce block diagram alliance semiconductor 2575 augusti ne dr i v e ? santa clara, ca 95054 ? t: 40 8-855-4900 ? f: 408-855-49 99 ? w w w . a ls c.com
july 2004 as91l1003u as91l1003u gateway functional descriptio n the ba si c structu r e of the as91l1 00 3u device i s sh o w n in figu re 1. the co re o f the device is the 16-sta t e ieee1149. 1 tap controlle r state machi ne. all acce sses to the internal registe r s of the as91l 1 003 u d e vice are controll ed via thi s state machin e durin g normal operatio n as pe r the ieee1149.1 stand ard. th e address se lection lo gic enabl es the as91l10 03 u to operate i n a multi- dro p environ ment within system ba ckpl ane. the add re ss sele ction logi c com pares t he scann ed ad dre ss to th e slot a ddress valu e pre s ente d o n the i/o of t he as91 l10 03u devi c e. the lsp park/unp ark logic p r ov ides control throug h in structio ns scanne d in unde r the ieee1149.1 proto c ol, to select which l sp will be placed into the active scan ch ain. the pa ss- throug h and lsp conne ction logi c select s the sign al path s f o r the lsp i eee1149.1 signal s. the device also suppo rts a pa ss-th r ou gh mode whi c h enabl es the primary ieee1149.1 signals to be routed to any of the lsps. this si gnal routing i s sele ctabl e vi a i/o pi ns on the as9 1l00 03 u device. the as91l 1 003 u op erati on is co ntroll ed via core blocks throu gh three cl osely cou p l ed state ma c h in es . f i g u r e- 2 sh ows th e de vic e s e le c t ion state ma chi n e. the as9 1 l100 3u will perfo rm a n address com pare on th e slot ad dre s s pre s ente d at its i/o a nd the valu e scan ned i n via the ieee1149.1. if the value matche s, then the as91l10 03 u beco m e s se lected a nd is ready for norm a l acce ss via ieee1149.1 co mma nds. if the address do e s not match then the d e vice will proceed to t he unselect ed mode, where it will remai n until the as91l100 3u is issu ed a goto w ait instructio n or a re set occurs via either trs t or the lsp_res e t pin. selec t e d single d e vi ce d e vi ce uns e l e ct ed sel e ct gro u p of devic e s selec t a l l de vi c e s wa it f o r s e lec t io n par k ed- tl r parked -rti park ed- pa useir un pa r k e d park ed- p ause d r figure 2 - as91l10 03 u selection lo gic state ma chine figure 3 - th e lsp park/unp ark state ma chi n e the lsp park/un park stat e machi ne control s the in se rtio n of the lsps into the curre n t active scan chai n. the ability to park the lsp in certain ieee1149.1 states, enable t he as91l1003u to perform several functi ons in clu d ing backpl ane int e rconn ect testing and ic bist. www .a lsc.com alliance semiconductor 2 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u as91l1003u detailed mode of operation addre ssing the as91 l10 03u dev i ce after a test-logi c-re set or po wer-u p , the as91l10 03 u device wil l be in its wait-for- s e lect ion st a t e wit h it s t d o pi n tri-st ated, thus avoiding con t ention in a multi-drop e n vironm ent. the as91l1 003 u device will re spon d to a device- sele ct sequ e n ce fo r a p a rticul ar add ress that is auto gen erated by third p a r ty tes t tools with res p ec t to the add re ss that is p r e - l oade d on its s(5..0) pin s . once this seque nce ha s be en com p leted, the as91l10 03 u device will resp ond to no rmal ieee 1149.1 in struction s . not e that addre s ses 60 -6 3 have been re serve d and the as91l10 03u devi c e will not respond if t he user sel e cts these addresse s. to be sel e ct ed, the as91 l100 3u devi c e sho u ld b e in the wait-fo r -sele c tion m ode whi c h can be entered into by issuin g an a s ynch ron o u s reset (th r ou g h the d e a s sertion of trst) o r by issuing syn c h r ono us reset (thro ugh the assertio n of tms for five c y c l es of tck). after the devic e has bee n sel e cted, it can be issu ed a goto w ait instru ction o r a reset of the as91l10 03 u device. the i n tern al i eee1149.1 st ate ma chin e of the as91l10 03u devi c e i s take n to the shift-ir pha se and th e requi red device-i d i s shifted into the instru ctio n regi ster . as the ieee1149.1 state machi ne pa sse s throu gh the upd a te-i r pha se, the add re ss i s matched to the value on t he s(5 - 0 ) pins on the as91l10 03 u device; if the valu es match then the as91 l10 03u devi c e i s sele cte d and is ready to receive any normal ieee1149.1 comm and. s(5-0 ) value ir (7 ? 0) val ue < 3a hex or 6 0 decim al xxvvvvvv table 1 - as 91l10 03 u dev i ce selection table www .a lsc.com alliance semiconductor 3 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u table 2 - as 91l10 03 u m u lti cas t gro up selection ta ble table 3 - as 91l10 03 u dev i ce regis t er des c ription selection mode binary addre ss function single addre s s mode xx00000 0 to xx11101 0 single as91l 1003 u sele cted the tdo of the device wil l be active broad - ca st mode xx11101 1 a l l acce ssible as91l10 03 u device s are sele cted for operation. tdo on all devices will be in highz multi-cast grou p 0 xx11110 0 a c c e s s a l l as91l10 03 u device that have bee n placed in grp0 by their mcg r conte n ts multi-cast grou p 1 xx11110 1 a c c e s s a l l as91l10 03 u device that have bee n placed in grp1 by their mcg r conte n ts multi-cast grou p 2 xx11111 0 a c c e s s a l l as91l10 03 u device that have bee n placed in grp2 by their mcg r conte n ts multi-cast grou p 3 xx11111 1 a c c e s s a l l as91l10 03 u device that have bee n placed in grp3 by their mcg r conte n ts regis t er nam e des c ription i n st ru ct ion regi ster a s91l10 03 u device ad dre ssi ng and in stru ctio n-de co de ieee std. 1149.1 required regi ster bounda ry- scan regi ster ieee std. 1149.1 required regi ster b y pass regi ster ieee std. 1149.1 required regi ster d e vice identification regi ster ieee std. 1149.1 optional regi ster user code regi ster ieee std. 1149.1 optional regi ster status regi ster as91l10 03 u device no n intrusive 8 - bit registe r pre load able from the i/o pins self tes t regi ster as91l10 03 u device spe c ific singl e bit regi ster for initiati ng self testing o n a pcb mode regi ster as91l10 03 u device lo cal-port config uratio n and control bi ts auto write regi ster as91l10 03 u device auto write feature en abl e regi ster local scan port as ync re set regi ster as91l10 03 u device asyn c reset regi ster for the lsps www .a lsc.com alliance semiconductor 4 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u table 4 - as 91l10 03 u dev i ce instruc t ion regis t er opcod es not e : all ins t ruc t ions ac t on a single selected as 91l10 03 u de v i ce only . * this instru ction cau ses the as9 1 l1 003 u to bec o me unselec ted and r e v e rt to th e wai t -for - selection s t ate. instructions hex o p - code binary op- code dat a re giste r b y p a s s f f 1 1 1 1 1 1 1 1 b y p a s s regi s t e r e x t e s t 0 0 0000 0 0 0 0 bounda ry-s c a n re giste r s a m p l e / p r e l o a d 8 1 1000 0 0 0 1 bounda ry-s can re giste r idco d e a a 1010 1 0 1 0 device i d e n t i f i c a t i o n regi st e r unpa r k e 7 1110 0 1 1 1 device i d e n t i f i c a t i o n regi st e r p a r k t l r c 5 1100 0 1 0 1 device i d e n t i f i c a t i o n regi st e r p a r k r t i 8 4 1000 0 1 0 0 device i d e n t i f i c a t i o n regi st e r p a r k p a u s e c 6 1 1 0 0 0 1 1 0 device i d e n t i f i c a t i o n regi st e r goto w ait* c 3 1100 0 0 1 1 device i d e n t i f i c a t i o n regi st e r modesele c t 8 e 1 0 0 0 1 1 1 0 m o d e regi s t e r mcg r sele c t 03 0000 0011 multi-cast g r oup regi ster. softreset 8 8 1 0 0 0 1 0 0 0 device i d e n t i f i c a t i o n regi st e r userco d e 9 7 1001 0 1 1 1 user pro g ra mmable 3 2 bit identification regi ster auto wr 98 1001 1000 auto write fe ature ena b le regi ster stest_pcb 99 1001 1001 single bit low pulse u s e d to initiate function on pcb (self_test pin) status_by t e 9 a 1001 1 0 1 0 user p r og ram m abl e statu s byte (user_ s tatus_ data pins) lsp_async_reset 9b 10011011 toggles lsp trst while maintaining the as91l1003u in the sele cted state. other undefi ned tbd tbd device identification regi st er www .a lsc.com alliance semiconductor 5 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u as91l1003u device register descriptions by pass register it is a mandatory singl e bit regi ster that can be conn ecte d betwe en pri m _tdi a nd p r im_t do of the as91l1003 u devi c e . multi-cast group regi ster this 2 - bit dat a regi ster e n able s the ho st system to pl a c e the as9 1l 1003 u into o ne of four distin ct addre s sable g r ou p s . mcg r re gis t er bit s [1..0] binar y selec t ion addr ess mc gr gr ou p 0 0 x x 1 1 1 1 0 0 g r p 0 0 1 x x 1 1 1 1 0 1 g r p 1 1 0 x x 1 1 1 1 1 0 g r p 2 1 1 x x 1 1 1 1 1 1 g r p 3 table 5 - mul t icas t group register ma pping note: th e mcg r is rese t to 00 upon r eceiv i ng trst or the entering of th e test-logic - reset sta t e . idcode re gister it is an optional 32-bit reg i ster that ca n be con n e c ted be tween prim _ t di and pri m _tdo of the as91l 1 003 u d e vice . the co nte n ts of the idco de regi ster will b e l oade d with the follo wing data when the as91l 10 03u ente r s test-logi c- re set or pa sse s throu gh captu r e - ir: "00000 000 00 0000 0010 000 0110 1101 111 " bits 0 to 11 indic a te alsc j e dec id value of: ?001 101 101 1 11? bits 12 to 2 7 indi cate th e pa rt num b e r of th e device: ?0 000 0000 0001 000 0? bits 28 to 31 indi cate th e revisio n of th e devi c e: ?000 0? usercode register the usercode i s a 32 -bit regi ster th at ca n be a ddressed via stand ard ieee1149.1 comm and s, whi c h a r e aut omatically ge nerate d by third pa rty test tools. the end u s e r ha s the ability to program the binary value that will be transmitted b a ck to the ho st via the userco de comm and; b y setting th e bina ry patte rn o n the userco de pins o n the as91l10 03 u d e vice. * the as91 l 1003 u is a c o mplete se c ond sourc e and pin for p i n replaceme n t of th e fire cron jts03 u dev i ce. www .a lsc.com alliance semiconductor 6 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u status_ b yte register the status _byte regist er on the as91l10 03 u device provides a me an s to sen s e the value on the user_st a tus_da ta pins on the as91l10 03u d e vice. this is an 8-b i t field whe r e the u s er ca n non -int rusively mo nitor sig nal s on the printe d circuit ca rd via the ieee1149.1 interface. the data in the re gister i s load ed ea ch time the state machin e pa sse s throu gh the captu r e - dr pha se. note: value i s positiv e lo gic. self_test register the as91 l 1 003 u devi c e sup port s a si ngle output pi n that can be co ntro lled via th e ieee1149.1 interface. w hen the i n struction is loade d into th e as91l 100 3 u in stru ction regi ster, a singl e bit data regi ster i s conne cted whi c h is set to zero when th e tap state machi ne e n te rs ca pture - d r . th is w ill c a u s e th e sel f _ t est pin to pu lse low fo r one cycle of t c k , durin g the upd a te-dr pha se. thi s low goi ng pul se can b e used to initiate self-te s ts on pcb?s in a ra ck via the jtag interface. lsp_asy n c_rst reg i ster the as91 l 1 003 u d e vice sup port s a s y n c reset te sts on the device s con n e c ted to the lsps. the stan da rd method of performi ng the s e test s by utilizing the p r im_t rst pi n ca nnot be use d a s it will cau s e the as91l10 03 u to d e select and all its internal re gisters to be re set. in orde r to enabl e asyn c re set t e sts on the l sp, the test tool sh ould inst ru ct t h e d e v i ce t o t o g g l e t h e lo cal sc an po rt reset pin s whi l e maintaini n g the set up i n formatio n in the as91 l100 3u. wh en the in struction i s loade d into the as91 l10 03u in stru cti on regi ster, a singl e bit data re giste r is co nne cte d whi c h i s alway s set to zero wh en t he tap state machi ne enters capture-dr. thi s wi ll cau s e the l sp trst pins to pul se low f o r one tck cycl e, durin g the upd a te- dr p has e. autow r register this i s a 3-bit regi ster that controls the p a ss- throug h of the jtag t e ch nolo g ies autowr ? sign al to an y local s c a n port. t he regi ster is reset to all zero s whe n e n tering the t e st-l ogi c- re set st at e. aut o wr regi ster (bit 2 ? bit 0) lsp 3 aut o wr sign al lsp 2 aut o wr sign al lsp 1 aut o wr sign al 000 high z high z high z 001 high z high z active 0 1 1 h i g h z a c t i v e a c t i v e 100 active high z high z 1 0 1 a c t i v e h i g h z a c t i v e 1 1 0 a c t i v e a c t i v e h i g h z 1 1 1 a c t i v e a c t i v e a c t i v e table 6 - autowr regis t er map p ing www .a lsc.com alliance semiconductor 7 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u mode_sel ect register the m ode _s elect re giste r allows th e l o c al scan port of the as91l10 03u to be co nne cted in variou s different co nfigura t ions. a lsp is sele cted for con n e c tion within t he scan ch ain by th e conte n ts of the mode_s ele c t regi ster. if the lo cal scan p o rt i s not pa rked i n a stable state, i . e.: pause - dr, pau s e - ir, run - te st- idle or test-logic-reset, it will be connected into the a c tive scan chain. if a ll lsps a r e p a rked i n a stable state, then the as91 l100 3u will perform a loopb ack of tdi->re g iste r->t do. mode_sele c t register (bit 7 -> bit 0 ) lsp configu r ation (if por t unp a rke d ) x x x 0 x 0 0 0 t d i - > r e g i ster->t d o x x x 0 x 0 0 1 t d i - > r e g i ster->lsp1->pa d->t d o x x x 0 x 0 1 0 t d i - > r e g i ster->lsp2->pa d->t d o x x x 0 x 0 1 1 t d i - > r e g i ster->lsp1 ->pa d->lsp2->p a d->tdo x x x 0 x 1 0 0 t d i - > r e g i ster->lsp3->pa d->t d o x x x 0 x 1 0 1 t d i - > r e g i ster->lsp1 ->pa d->lsp3->p a d->tdo x x x 0 x 1 1 0 t d i - > r e g i ster->lsp2 ->pa d->lsp3->p a d->tdo x x x 0 x 1 1 1 t d i - > r e g i ster->lsp1->pa d->lsp2->p a d->lsp3->pad->tdo table 7 - mo de select re gister ma pping x = don?t ca re regis t er = a s 91l10 03 u d e vice in stru ction regi ste r or any of the as91l10 03 u d e vice test dat a regi sters. pad = in se rtion of a 1-bit regist e r for dat a synchro n ization. upo n enteri n g test-logi c-re set, the re gist er bit s will be loade d wi th ?0000 000 ?. www .a lsc.com alliance semiconductor 8 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u pass-through support with in the as91l1003u device the as91 l 1 003 u d e vice sup port s a p a ss- thro ugh mo de whe r e t he p r ima r y or ma ster ieee1149.1 jtag si gnal s ca n be ro uted to any one of the l sps. when t h is mod e is a c tivated, the ?de bug e nab le? si gnal fo r that lsp will go a c tive, w h ic h c a n be us e d to p l a c e a pr oc ess o r su ch as the mpc82 60 into b d m (ba c kgro und deb ug mode ) if req u ired. if no p r ocesso rs are pre s e n t in the lsp, the pass-t hro u g h mode can be used to assist in the gene ration of the test vectors o r memory te sts for the devi c es th at are li nke d into the sele cted lsp. the pass-throug h feature ha s the effect of simplifying th e test ve cto r gene ration for the lsp, as it also h a s the effe ct of rem o ving the as91l1 003 u device from the test vecto r gene ration p r oce s s. pa ss_thru_en ab le pa ss_thru_sel( 1 ) pa ss_thru_sel( 0 ) activ e lsp h i g h x x n o r m a l op e r a t i o n l o w l o w l o w l s p 1 l o w l o w h i g h l s p 2 l o w h i g h l o w l s p 3 table 8 ? pa ss-t h rough mode in as9 1 l100 3u n o te: w h en pa ss_thru_en ab le enable is deas serted ( l ogic ? 1 ?) , t h en t h e lsps are under contr o l of th e as91l 100 3u dev i ce lo gic. when p a ss_thru_ e nable is a sser ted (logi c ?0 ?) and if an invalid combinat ion is present ed on the pa ss_thru_sel lines, t h en all lsps are tri-s t ated. www .a lsc.com alliance semiconductor 9 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u signal descriptio n pin name pin type pin num be r lqfp pin num be r fpbg a description stable sign al s states, with device unsele c ted a nd active output s on the device lsp1_tck out 31 h4 ieee1149.1 test cl ock on local scan port 1 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 00. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k lsp1_tms out 32 j4 ieee1149.1 test mod e select on local scan p o rt 1 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 00. this pin i s tri-stated for all other combi nation s . logi c '1' lsp1_tdo out 35 h5 ieee1149.1 test data ou t on local scan port 1 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 00. this pin i s tri-stated for all other combi nation s . logi c '1' lsp1_tdi in 33 k4 ieee1149.1 test data in on lo cal scan port 1 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 00. lsp1_trst out 29 k3 ieee1149.1 test reset on local scan port 1 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 00. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st www .a lsc.com alliance semiconductor 10 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u pin name pin type pin num be r lqfp pin num be r fpbg a description stable sign al s states, with device unsele c ted a nd active output s on the device lsp1_autow r out 30 j3 flash, me mor y auto-write on lo cal scan port 1 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 00. this pin i s tri-stated for all other combi nation s . logi c '1' lsp1_de out 28 j2 pass-t hro u g h deb ug ena b le output on lo cal sca n port 1. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[1:0] = 0 0. this pin i s hig h for all other combi nation s . logi c '1' lsp2_tck out 41 j6 ieee1149.1 test cl ock on local scan port 2 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 01. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k lsp2_tms out 42 h6 ieee1149.1 test mod e select on local scan p o rt 2 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 01. this pin i s tri-stated for all other combi nation s . logi c '1' lsp2_tdo out 45 j7 ieee1149.1 test data ou t on local scan port 2 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 01. this pin i s tri-stated for all other combi nation s . logi c '1' www .a lsc.com alliance semiconductor 11 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u pin name pin type pin num be r lqfp pin num be r fpbg a description stable sign al s states, with device unsele c ted a nd active output s on the device lsp2_tdi in 44 k7 ieee1149.1 test data in on lo cal scan port 2 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 01. lsp2_trst out 37 k5 ieee1149.1 test reset on local scan port 2 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 01. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st lsp2_autow r out 40 k6 flash, me mor y auto-write on lo cal scan port 2 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 01. this pin i s tri-stated for all other combi nation s . logi c '1' lsp2_de out 36 j5 pass-t hro u g h deb ug ena b le output on lo cal sca n port 2. active low ou tput when pass_thru_enable = 0 and pass_thru_sel[1:0] = 0 1. this pin i s hig h for all other combi nation s . logi c '1' lsp3_tck out 49 k9 ieee1149.1 test cl ock on local scan port 3 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 10. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t c k www .a lsc.com alliance semiconductor 12 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u pin name pin type pin num be r lqfp pin num be r fpbg a description stable sign al s states, with device unsele c ted a nd active output s on the device lsp3_tms out 50 k10 ieee1149.1 test mod e select on local scan p o rt 3 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 10. this pin i s tri-stated for all other combi nation s . logi c '1' lsp3_tdo out 53 h10 ieee1149.1 test data ou t on local scan port 3 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 10. this pin i s tri-stated for all other combi nation s . logi c '1' lsp3_tdi in 52 j10 ieee1149.1 test data in on lo cal scan port 3 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 10. lsp3_trst out 47 j8 ieee1149.1 test reset on local scan port 3 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 10. this pin i s tri-stated for all other combi nation s . buffered version of signal p r e s ent on prim ary t r st lsp3_lsp_ autowr out 48 k8 flash, me mor y auto-write on lo cal scan port 3 whe n pass_thru_enable is high. pin is in pass-th roug h mo de wh en pass_thru_enable = 0 and pass_thru_sel[1:0] = 10. this pin i s tri-stated for all other combi nation s . logi c '1' www .a lsc.com alliance semiconductor 13 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
www.alsc.com alliance semiconductor 14 july 2004 as91l1003u 2003, 2004 ? copyright alliance semiconductor corporation. all rights reserved. pin name pin type pin number lqfp pin number fpbga description stable signals states, with device unselected and active outputs on the device lsp3_de out 46 h7 pass-through debug enable output on local scan port 3. active low output when pass_thru_enable = 0 and pass_thru_sel[1:0] =10. this pin is high for all other combinations. logic '1' prim_tck in 87 a6 ieee1149.1 primary test clock input. prim_tms in 21 g2 ieee1149.1 primary test mode select input. prim_tdo out 20 g1 ieee1149.1 primary test data output. this pin is tri-stated when as91l1003 is not selected. highz prim_tdi in 19 g3 ieee1149.1 primary test data input prim_trst in 22 h2 ieee1149.1 primary test reset input. this active low asynchronous reset input signal places as91l1003u in wait-for-selection state. prim_autowr in 16 f1 primary auto-write input controlled by test equipment to shorten flash memory programming. s[5:0] in 8,7,6,5,100, 99 d2,d1,d3,c2, b2,a2 slot address (5:0) inputs. used to set address at which as91l1003u will respond; typically set by hardwired connection on the backplane. *toe in 88 b6 test output enable input. tri-states all lsps, when asserted low. lsp_reset_n in 14 f4 local scan port reset input. active low resets as91l1003u to ?wait-for-selection? state and pulses all lsp trst output pins to low. this resets all devices with trst function; typically this signal would be connected to a power-on-reset function.
july 2004 as91l1003u pin name pin type pin num be r lqfp pin num be r fpbg a description stable sign al s states, with device unsele c ted a nd active output s on the device as91l10 03 u_ selected o u t 2 5 k 1 as91l10 03 u_selecte d ou t p u t . active low wh en as91l1 00 3u is sele cted; typically used to control off board bufferi ng. lsp_enabl e out 24 j1 local scan p o rt enable o u tput. a ctive low ou tput when as 91l1 003 u is s e lec t ed; ty pic a lly us ed t o s e t ieee1149.1 complian c e e n able pin s on devices. user co de [15:0] i n 6 4 , 6 5 , 6 7 , 6 8 ,69,70,71,7 2,75,76,77, 78,79,80,8 1 ,83 (msb- lsb) e9,e10,e8,e7 ,d9,d1 0,d8, c 9,c10,b10,b 9 ,a9,a8,b8,a7 , b7 (msb- lsb) user/boa rd identif icatio n inputs. used to esta blish b oard type and revis i on s o as to ens ure c o rrec t ieee1149.1 test vecto r set s are applie d. user_status _ byte[7:0] in 84, 85, 92, 93, 94, 96, 97, 98 (msb-lsb) c7,c 6,c5, c 4 , b4,a4,b3,a3( msb-lsb) user_statu s_byte inputs. used to provi de statu s info rmation of the pcb und er test ba ck to the test maste r via the ieee1149.1 bus. eight sign als level s can be mo nitored a nd then rep o rte d via the ieee1149.1 b u s in a non intru s ive mann er. self_test out 27 k2 provide s a lo w goin g outp u t pulse unde r co mma nd from the ieee1149.1 bus, which ca n be used to s t art s e lf-tes t func tions on a pcb. logi c '1' pass_thru_ enable in 9 e4 pass_thru enable input . active high di sabl es pa ss-thro ugh mode. active low en able s pass-t hrou gh mode. pass_thru_ sel[1:0] in 12,10 e1,e3 pass_thru select inputs. used to sel e ct active routin g of pass- thro ugh p o rt s ena bled by active low on pass_thru_enable pin. 00 = lsp1 01 = lsp 10 = lsp3 www .a lsc.com alliance semiconductor 15 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u pin name pin type pin num be r lqfp pin num be r fpbg a description stable sign al s states, with device unsele c ted a nd active output s on the device gnd power 38, 86, 11, 26, 43, 59, 74, 95, 2, 17, 54, 90 d6, g5, c3, d7, e5, f6, g4,h8, h9, j 9 ,b1, a5, f2 grou nd pin s . vcc power 39, 91, 3, 18, 34, 51, 66, 82,23, 55, 56 d5, g6, c8, d4, e6, f5, g7, h3,g9, h1 vcc pin s . asic_test_ en in 89 b5 facto r y test_ e nable input. this pin sho u l d be left unconne cted. asic_tck in 62 f8 ieee1149.1 asic test cl ock input. asic_tms in 15 f3 ieee1149.1 asic test mode sele ct input. asic_tdo out 73 a10 ieee1149.1 asic test cl ock output. asic_tdi in 4 a1 ieee1149.1 asic test cl ock input. no conn ect s 1,13,63,61, 60,58,57 c1,e2,f7,f10 ,f9,g8,g10 table 10 - as91l00 03 u signal descr iption www .a lsc.com alliance semiconductor 16 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u absolute maximum ratings parameter maximum range supply voltage (vcc) -0.3v to 5.5v dc inp u t voltage (vi) -0.5v to vcc +0.5v max sink cu rrent whe n vi = -0.5v -20ma max sou r ce current wh en vi = vcc + 0. 5v +20ma max jun c tion tempe r ature with power a pplied tj +12 5 deg ree s c max storage temperature -55 to +150 d egre e c table 11 - absolute m axi mum rating s note: str ess abov e the stated maximu m v a lues ma y cause irreparable dam a ge to the d e v i ce. corre ct op er ation of the dev i ce at these v a lues is not guar a nte e d. recommended operating conditions parameter opera t ing range supply voltage (vcc) 3.0v to 3.6v input voltage (vi) 0v to vcc output voltag e (vo) 0v to vcc operating te mperature (t a) comm ercial 0 c to 70 c industri a l (ta ) -40 de g c to +85 d eg c, 3. 00v to 3.6v table 12 - recommende d opera t ing conditio n s www .a lsc.com alliance semiconductor 17 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u ac electrical characteristics lsp s i g n a l tpd tco toe th tc l tc w tch tc k td o td i tm s hi g h z hi g h z tsu figure 4 - as91l10 03 u ac timing diagram symbol parameter min max units tcw tck clo c k pu lse wi dth 100 - ns tch tck pul se wi dth high 50 - ns tcl tck pul se wi dth low 50 - ns tsu tck setup time 30 - ns th tck hol d time 40 - ns toe neg edg e tck to valid data enabl e 20 - ns tco neg edg e tck to valid data 15 - ns tpd pass th rou g h mode prima r y/lsp delay - 10 ns table 9 - as 91l10 03 u ac timing information www .a lsc.com alliance semiconductor 18 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u dc electrical characteristics sy mbol parameter min max conditio n v ih minimum hi g h input voltage 2.0 5.25 v il maximum lo w input voltage -0.3v 0.8v sy mbol parameter value conditio n v oh minimum hi gh output voltage 2.4v ioh=2 4 ma or 8ma as defined by pi n v ol minimum lo w output voltage 0.4v iol=24ma o r 8ma as defined by pi n i oz tris tate output leak age -10 o r 10 ma i cc maximum qui ece nnt s u pp ly c u rr ent 2ma i ccd maximum dynamic s u pp ly c u rr ent 80ma tck freq e q u a l to 10 mhz table 13 - as91l10 03 u dc elec trica l charac teris t ics packaging information the as91l1 0 03u i s availa ble in a 100 -p in lqfp or a 100-pin fpb g a lead free packa ge. d1 sq u a r e 1 d s qua r e 3 d 1 ba si c 14 . 0 0 d ba si c 18 . 0 0 l 0. 15 0. 6 0 a 2 m i n no m m a x 1 . 35 1 . 40 1. 4 5 l1 re f 1. 0 0 a ma x . 1. 6 0 b mi n m a x 0 . 1 7 0 . 2 7 a 1 0. 0 5 0 . 15 e ba si c 0. 5 0 j e d e c re f # ms - 0 2 6 cc c ma x 0. 0 8 dd d no m 0. 0 8 sym b o l 100 le a d to l . le a d s mi n m a x not e s : 1 . a l l l i n e a r d i m e n s io n s a r e i n m i l l i m e t e r s . 2 . pl as t i c bo dy d i m e n s i o ns do n o t i n c l u d e f l as h o r pr o t usi o n . m ax al l o w a bl e 0 . 2 5 per si de. 3 . l ead c o un t o n d r a w i n g n o t re presentat i ve o f a c tual packag e. 3. m a 0.2 5 0 . 09/0.20 t y p 0 - 7 typ l l1 b a1 - c - cc c l e ad co pl a n a r i t y al a l al a- b s d s a2 a 12 n o m 12 n o m e figure 5 - l q fp-1 00 www .a lsc.com alliance semiconductor 19 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u r e visions r e v . d e s c r i p t i o n e c n d a t e a initial document release. 91253 12-04- 01 b updated ball cop l anarit y limits from 0.20mm to 0.15 mm. d e a b 2 c 0.15 c d1 e1 c d g h i k 1 2 3 4 5 6 7 8 9 1 0 f e b a b 0 . 2 5 m c 0 . 2 5 m c a b dimensions s y mb o l m i n . no m . m a x . a - - - - 1 . 7 0 a 1 0 . 3 0 - - - - a 2 0 . 2 5 - - 1 . 1 0 b 0 . 5 0 0 . 6 0 0 . 7 0 d 1 1 . 0 0 b s c d 1 9 . 0 0 b s c e 1 1 . 0 0 b s c e 1 9 . 0 0 b s c e 1 . 0 0 packag e num ber fbg a 010 0-11 f j e dec ref # mo-19 2 var. a a c-1 figure 6 - fp bg a-1 00 www .a lsc.com alliance semiconductor 20 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u device select or guid e and orde rin g information as91l x xxx u u - cc pp - temp - l al i a n c e s emi c ond uc t o r syste m so lu tio n d e vice fa mily 1001 1002 1003 1006 pro duc t v e rs i o n s = s t andar d u = 16 - b it use r cod e bu = 8- bi t s t at us / u s e r c ode e = e nhanc ed c = com mer c i al (0 t o 70 d egrees c) i = i ndus t r i a l (- 40 t o 85 deg rees c) pa cka ge l 100 = 10 0 pi n lqf p f 100 = 1 00 pi n f p bga c l o ck spe e d 10 = 10 m h z tck 40 = 40 m h z tck b l ank = le aded f = l ead f r ee g = green figure 7 - part numbe r ing guide www .a lsc.com alliance semiconductor 21 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u part number des c ription as91l10 03 u ? 10l10 0-c 3-port jtag gateway, 100-pin l q fp packa ge, co mmercial as91l10 03 u ? 10l10 0-cf 3-port jtag gateway, 100-pin l q fp packa ge, co mmercial, lea d free as91l10 03 u ? 10l10 0-i 3-port jtag gateway, 100-pin l q fp packa ge, ind u strial as91l10 03 u ? 10l10 0-if 3-port jtag gateway, 100-pin l q fp packa ge, ind u strial, lea d free as91l10 03 u ? 10f100 -c 3-port jtag gateway, 100-pin fpbga packa ge, co mmercial as91l10 03 u ? 10f100 -cg 3-port jtag gateway, 100-pin fpbga , comm ercial, gree n pa ckag e as91l10 03 u ? 10f100 -i 3-port jtag gateway, 100-pin fpbga packa ge, ind u strial as91l10 03 u ? 10f100 -ig 3-port jtag gateway, 100-pin fpbga , indu strial, gre en pa ckage as91l10 03 u ? 40l10 0-cf 3-port jtag gateway, 100-pin l q fp packa ge, co mmercial, lea d free, 40 mhz tck as91l10 03 u ? 40l10 0-if 3-port jtag gateway, 100-pin l q fp packa ge, ind u strial, lea d free, 40 mhz tck as91l10 03 u ? 40f100 -cg 3-port jtag gateway, 100-pin fpbga , comm ercial, gree n pa ckag e, 40 mhz tck as91l10 03 u ? 40f100 -ig 3-port jtag gateway, 100-pin fpbga , indu strial, gre en pa ckage, 40 mhz tck table 14 - valid part number combinations www .a lsc.com alliance semiconductor 22 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u packag e options dev i ce master des c ription fpbg a-1 00 (1mm pitch) lqfp -100 as91l10 01 jtag te st controlle r x x as91l10 02 jtag te st seque ncer x x as91l10 03 u 3 - p o r t g a t e w a y x x as91l10 06b u 6 - p o r t g a t e w a y x x table 15 - jt ag contr o ller produc t family www .a lsc.com alliance semiconductor 23 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1003u www .a lsc.com alliance semiconductor 24 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.

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